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    ISPASS
    2007
    IEEE
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    DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving
    15 years 9 months ago
    DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving
    Download  www.ece.uic.edu
    We have studied DRAM-level prefetching for the fully buffered DIMM (FB-DIMM) designed for multi-core processors. FB-DIMM has a unique two-level interconnect structure, with FB-DIM...
    Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Zhao Zhan...
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