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128
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IPPS
2005
IEEE
112
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Distributed And Parallel Com...
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IPPS 2005
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Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores
15 years 8 months ago
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www-scf.usc.edu
The use of pipelined floating-point arithmetic cores to create high-performance FPGA-based computational kernels has introduced a new class of problems that do not exist when usi...
Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna
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