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134
Voted
SBCCI
2003
ACM
94views VLSI» more  SBCCI 2003»
15 years 10 months ago
A New Pipelined Array Architecture for Signed Multiplication
– We present a new architecture for signed multiplication which maintains the pure form of an array multiplier, exhibiting a much lower overhead than the Booth architecture. This...
Eduardo A. C. da Costa, Sergio Bampi, José ...
134
Voted
GLVLSI
2003
IEEE
132views VLSI» more  GLVLSI 2003»
15 years 10 months ago
Power-aware pipelined multiplier design based on 2-dimensional pipeline gating
Power-awareness indicates the scalability of the system energy with changing conditions and quality requirements. Multipliers are essential elements used in DSP applications and c...
Jia Di, Jiann S. Yuan