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ASAP
2007
IEEE
153views Hardware» more  ASAP 2007»
13 years 2 months ago
Performance Evaluation of Adaptive Routing Algorithms for achieving Fault Tolerance in NoC Fabrics
Commercial designs are integrating from 10 to 100 embedded functional and storage blocks in a single system on chip (SoC) currently, and the number is likely to increase significa...
Haibo Zhu, Partha Pratim Pande, Cristian Grecu
ASAP
2007
IEEE
118views Hardware» more  ASAP 2007»
13 years 4 months ago
Evaluation of a Tightly Coupled ASIP / Co-Processor Architecture Used in GNSS Receivers
This paper presents the enhancement of an ASIP’s floating point performance by coupling of a co-processor and adding of special instructions. Processor hardware modifications an...
Götz Kappen, S. el Bahri, O. Priebe, Tobias G...
ASAP
2007
IEEE
134views Hardware» more  ASAP 2007»
13 years 4 months ago
Methodology and Toolset for ASIP Design and Development Targeting Cryptography-Based Applications
Network processors utilizing general-purpose instruction-set architectures (ISA) limit network throughput due to latency incurred from cryptography and hashing applications (AES, ...
David Montgomery, Ali Akoglu
ASAP
2007
IEEE
109views Hardware» more  ASAP 2007»
13 years 4 months ago
Long Live Small Fan-in Majority Gates Their Reign Looks Like Coming!
This paper explores the reliability of three different minimum fan-in majority gates full adder (FA) designs, and compares them to the performance of a standard XOR-based FA. The ...
Walid Ibrahim, Valeriu Beiu
ASAP
2007
IEEE
175views Hardware» more  ASAP 2007»
13 years 4 months ago
Scalable Multi-FPGA Platform for Networks-On-Chip Emulation
Interconnect validation is an important early step toward global SoC (System-On-Chip) validation. Fast performances evaluation and design space exploration for NoCs (Networks-On-C...
Abdellah-Medjadji Kouadri-Mostefaoui, Benaoumeur S...
ASAP
2007
IEEE
135views Hardware» more  ASAP 2007»
13 years 4 months ago
An Efficient SIMD Architecture with Parallel Memory for 2D Cosine Transforms of Video Coding
Jianying Peng, Xing Qin, Dexian Li, Xiaolang Yan, ...
ASAP
2007
IEEE
112views Hardware» more  ASAP 2007»
13 years 4 months ago
Scheduling Register-Allocated Codes in User-Guided High-Level Synthesis
In high-level synthesis, as for compilers, an important question is when register assignment should take place. Unlike compilers for which the processor architecture is given, syn...
Alain Darte, C. Quinson
ASAP
2007
IEEE
104views Hardware» more  ASAP 2007»
13 years 4 months ago
Hardware Acceleration for 3-D Radiation Dose Calculation
Abstract— The problem of calculating accurate dose distributions lies in the heart of modern radiation therapy for cancer treatment. Software implementations of dose calculation ...
Bo Zhou, Xiaobo Sharon Hu, Danny Z. Chen, Cedric X...
ASAP
2007
IEEE
123views Hardware» more  ASAP 2007»
13 years 4 months ago
Estimating Area Costs of Custom Instructions for FPGA-based Reconfigurable Processors
FPGA (Field Programmable Gate Array) based reconfigurable processor has been shown to meet the increasingly challenging performance targets and shorter time-to-market pressures. I...
Siew Kei Lam, Thambipillai Srikanthan
ASAP
2007
IEEE
116views Hardware» more  ASAP 2007»
13 years 4 months ago
The Design of a Novel Object-oriented Processor : OOMIPS
A novel object-oriented processor is proposed in this paper, which provides support for object addressing, message passing and dynamic memory management. Object running on this pr...
Weixing Ji, Feng Shi, Baojun Qiao, Muhammad Kamran