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ATVA
2009
Springer
97views Hardware» more  ATVA 2009»
13 years 5 months ago
Memory Usage Verification Using Hip/Sleek
Embedded systems often come with constrained memory footprints. It is therefore essential to ensure that software running on such platforms fulfils memory usage specifications at c...
Guanhua He, Shengchao Qin, Chenguang Luo, Wei-Ngan...
ATVA
2009
Springer
142views Hardware» more  ATVA 2009»
13 years 8 months ago
TAPAAL: Editor, Simulator and Verifier of Timed-Arc Petri Nets
TAPAAL is a new platform independent tool for modelling, simulation and verification of timed-arc Petri nets. TAPAAL provides a stand-alone editor and simulator, while the verifica...
Joakim Byg, Kenneth Yrke Jørgensen, Jir&iac...
ATVA
2009
Springer
141views Hardware» more  ATVA 2009»
13 years 8 months ago
Formal Verification for High-Assurance Behavioral Synthesis
We present a framework for certifying hardware designs generated through behavioral synthesis, by using formal verification to certify the associated synthesis transformations. We ...
Sandip Ray, Kecheng Hao, Yan Chen, Fei Xie, Jin Ya...
ATVA
2009
Springer
99views Hardware» more  ATVA 2009»
13 years 8 months ago
CLAN: A Tool for Contract Analysis and Conflict Discovery
Abstract. As Service-Oriented Architectures are more widely adopted, it becomes more important to adopt measures for ensuring that the services satisfy functional and non-functiona...
Stephen Fenech, Gordon J. Pace, Gerardo Schneider
ATVA
2009
Springer
146views Hardware» more  ATVA 2009»
13 years 8 months ago
Specification Languages for Stutter-Invariant Regular Properties
We present specification languages that naturally capture exactly the regular and -regular properties that are stutter invariant. Our specification languages are variants of the cl...
Christian Dax, Felix Klaedtke, Stefan Leue
ATVA
2009
Springer
106views Hardware» more  ATVA 2009»
13 years 9 months ago
Verifying VLSI Circuits
Mark R. Greenstreet
ATVA
2009
Springer
117views Hardware» more  ATVA 2009»
13 years 10 months ago
UnitCheck: Unit Testing and Model Checking Combined
Code model checking is a rapidly advancing research topic. However, apart from very constrained scenarios (e.g., verification of device drivers by Slam), the code model checking t...
Michal Kebrt, Ondrej Sery
ATVA
2009
Springer
137views Hardware» more  ATVA 2009»
13 years 10 months ago
State Space Reduction of Linear Processes Using Control Flow Reconstruction
Abstract. We present a new method for fighting the state space explosion of process algebraic specifications, by performing static analysis on an intermediate format: linear proc...
Jaco van de Pol, Mark Timmer
ATVA
2009
Springer
142views Hardware» more  ATVA 2009»
13 years 10 months ago
Synthesis of Fault-Tolerant Distributed Systems
Abstract. A distributed system is fault-tolerant if it continues to perform correctly even when a subset of the processes becomes faulty. Faulttolerance is highly desirable but oft...
Rayna Dimitrova, Bernd Finkbeiner