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DAC
2012
ACM
11 years 6 months ago
Equivalence checking for behaviorally synthesized pipelines
Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing hardware designs with acceptable latency and throughput. However, it is a complex ...
Kecheng Hao, Sandip Ray, Fei Xie
ASPDAC
2012
ACM
253views Hardware» more  ASPDAC 2012»
12 years 2 days ago
An integrated and automated memory optimization flow for FPGA behavioral synthesis
Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...
Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong
DT
2010
99views more  DT 2010»
13 years 4 months ago
CEDA Currents
specified at levels of abstraction higher than the Register Transfer Level (RTL) in hardware description. The essential feature of a behavioral description is that, the designer on...
ISSS
1995
IEEE
98views Hardware» more  ISSS 1995»
13 years 7 months ago
On the use of VHDL-based behavioral synthesis for telecom ASIC design
higher levels of abstraction, due to the still increasing design complexities that can be expected in the near future. Behavioral synthesis can play a key role in this prospect, as...
Mark Genoe, Paul Vanoostende, Geert van Wauwe
ICCAD
1995
IEEE
135views Hardware» more  ICCAD 1995»
13 years 8 months ago
An iterative improvement algorithm for low power data path synthesis
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...
Anand Raghunathan, Niraj K. Jha
DAC
2000
ACM
13 years 8 months ago
Watermarking while preserving the critical path
In many modern designs, timing is either a key optimization goal and/or a mandatory constraint. We propose the first intellectual property protection technique using watermarking ...
Seapahn Meguerdichian, Miodrag Potkonjak
ICCAD
2000
IEEE
124views Hardware» more  ICCAD 2000»
13 years 8 months ago
A Methodology for Verifying Memory Access Protocols in Behavioral Synthesis
— Memory is one of the most important components to be optimized in the several phases of the synthesis process. ioral synthesis, a memory is viewed as an abstract construct whic...
Gernot Koch, Taewhan Kim, Reiner Genevriere
DATE
2010
IEEE
193views Hardware» more  DATE 2010»
13 years 9 months ago
Coordinated resource optimization in behavioral synthesis
Abstract—Reducing resource usage is one of the most important optimization objectives in behavioral synthesis due to its direct impact on power, performance and cost. The datapat...
Jason Cong, Bin Liu, Junjuan Xu
DATE
2003
IEEE
122views Hardware» more  DATE 2003»
13 years 9 months ago
Synthesis of Complex Control Structures from Behavioral SystemC Models
In this paper we present the results of a set of experiments we conducted in order to evaluate the viability of the behavioral synthesis, relying on the tools available at the mom...
Francesco Bruschi, Fabrizio Ferrandi
ISCAS
2006
IEEE
119views Hardware» more  ISCAS 2006»
13 years 10 months ago
Scheduling and binding for low gate leakage nanoCMOS datapath circuit synthesis
In this paper we present two polynomial time-complexity heuristic algorithms for optimization of gate-oxide leakage (tunneling current) during behavioral synthesis through simulta...
Saraju P. Mohanty, Elias Kougianos, Ramakrishna Ve...