Sciweavers

CDES
2006
158views Hardware» more  CDES 2006»
13 years 7 months ago
A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs
In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier des...
Himanshu Thapliyal, Vishal Verma, Hamid R. Arabnia
ARITH
2005
IEEE
14 years 3 days ago
N-Bit Unsigned Division via N-Bit Multiply-Add
Integer division on modern processors is expensive compared to multiplication. Previous algorithms for performing unsigned division by an invariant divisor, via reciprocal approxi...
Arch D. Robison