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126
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ASPDAC
2007
ACM
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ASPDAC 2007
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Symbolic Model Checking of Analog/Mixed-Signal Circuits
15 years 6 months ago
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www.async.ece.utah.edu
This paper presents a Boolean based symbolic model checking algorithm for the verification of analog/mixedsignal (AMS) circuits. The systems are modeled in VHDL-AMS, a hardware des...
David Walter, Scott Little, Nicholas Seegmiller, C...
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