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104
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ASPDAC
2006
ACM
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ASPDAC 2006
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Cycle error correction in asynchronous clock modeling for cycle-based simulation
15 years 8 months ago
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www.cecs.uci.edu
— As the complexity of SoCs is increasing, hardware/software co-verification becomes an important part of system verification. C-level cycle-based simulation could be an efficien...
Junghee Lee, Joonhwan Yi
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