Sciweavers

DSN
2011
IEEE
12 years 10 months ago
Transparent dynamic binding with fault-tolerant cache coherence protocol for chip multiprocessors
—Aggressive technology scaling causes chip multiprocessors increasingly error-prone. Core-level faulttolerant approaches bind two cores to implement redundant execution and error...
Shuchang Shan, Yu Hu, Xiaowei Li
DAC
2011
ACM
12 years 10 months ago
DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chips
As transistor dimensions continue to scale deep into the nanometer regime, silicon reliability is becoming a chief concern. At the same time, transistor counts are scaling up, ena...
Andrew DeOrio, Konstantinos Aisopos, Valeria Berta...
TPDS
2002
90views more  TPDS 2002»
13 years 10 months ago
Specifying and Verifying a Broadcast and a Multicast Snooping Cache Coherence Protocol
Daniel J. Sorin, Manoj Plakal, Anne Condon, Mark D...
TC
1998
13 years 10 months ago
Design Verification of the S3.mp Cache-Coherent Shared-Memory System
—This paper describes the methods used to formulate and validate the memory subsystem of the cache-coherent Sun Scalable emory MultiProcessor (S3.mp) at three levels of abstracti...
Fong Pong, Michael C. Browne, Gunes Aybay, Andreas...
AMAST
2008
Springer
14 years 7 days ago
The Verification of the On-Chip COMA Cache Coherence Protocol
This paper gives a correctness proof for the on-chip COMA cache coherence protocol that supports the Microgrid of microtheaded architecture, a multi-core architecture capable of in...
Thuy Duong Vu, Li Zhang, Chris R. Jesshope
ICPP
1991
IEEE
14 years 1 months ago
Cache Coherence on a Slotted Ring
-- The Express Ring is a new architecture under investigation at the University of Southern California. Its main goal is to demonstrate that a slotted unidirectional ring with very...
Luiz André Barroso, Michel Dubois
CHARME
2001
Springer
162views Hardware» more  CHARME 2001»
14 years 1 months ago
Parameterized Verification of the FLASH Cache Coherence Protocol by Compositional Model Checking
We consider the formal verification of the cache coherence protocol of the Stanford FLASH multiprocessor for N processors. The proof uses the SMV proof assistant, a proof system ba...
Kenneth L. McMillan
ICPP
1994
IEEE
14 years 2 months ago
A Distributed Cache Coherence Protocol for Hypercube Multiprocessors
- This paper proposes a distributed directory cache coherence protocol and compares the performance of the proposed protocol with fully mapped and single linked list protocols for ...
Yeimkuan Chang, Laxmi N. Bhuyan, Akhilesh Kumar
ASPLOS
1996
ACM
14 years 2 months ago
Shasta: A Low Overhead, Software-Only Approach for Supporting Fine-Grain Shared Memory
This paper describes Shasta, a system that supports a shared address space in software on clusters of computers with physically distributed memory. A unique aspect of Shasta compa...
Daniel J. Scales, Kourosh Gharachorloo, Chandramoh...
HPCA
1998
IEEE
14 years 2 months ago
Hardware for Speculative Run-Time Parallelization in Distributed Shared-Memory Multiprocessors
Run-time parallelization is often the only way to execute the code in parallel when data dependence information is incomplete at compile time. This situation is common in many imp...
Ye Zhang, Lawrence Rauchwerger, Josep Torrellas