96
Voted
SC
2009
ACM
15 years 7 months ago
2009
ACM
We present ECC FIFO, a mechanism enabling two-tiered last-level cache error protection using an arbitrarily strong tier-2 code without increasing on-chip storage. Instead of addin...
115
Voted
EUROSYS
2007
ACM
15 years 9 months ago
2007
ACM
The major chip manufacturers have all introduced chip multiprocessing (CMP) and simultaneous multithreading (SMT) technology into their processing units. As a result, even low-end...
86
Voted
HPCA
2007
IEEE
16 years 1 months ago
2007
IEEE
Caches are organized at a line-size granularity to exploit spatial locality. However, when spatial locality is low, many words in the cache line are not used. Unused words occupy ...