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114
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ICCAD
2008
IEEE
147
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ICCAD 2008
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Overlay aware interconnect and timing variation modeling for double patterning technology
15 years 11 months ago
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www.cerc.utexas.edu
— As Double Patterning Technology (DPT) becomes the only solution for 32-nm lithography process, we need to investigate how DPT affects the performance of a chip. In this paper, ...
Jae-Seok Yang, David Z. Pan
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