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111
Voted
ICCAD
2008
IEEE
117
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ICCAD 2008
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A novel sequential circuit optimization with clock gating logic
15 years 9 months ago
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cad63.cs.nthu.edu.tw
— To save power consumption, it has been shown that the clock signal can be gated without changing the functionality under certain clock-gating conditions. We observe that the cl...
Yu-Min Kuo, Shih-Hung Weng, Shih-Chieh Chang
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