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ASPDAC
2012
ACM
247views Hardware» more  ASPDAC 2012»
12 years 3 months ago
Through-silicon-via-induced obstacle-aware clock tree synthesis for 3D ICs
— In this paper, we present an obstacle-aware clock tree synthesis method for through-silicon-via (TSV)-based 3D ICs. A unique aspect of this problem lies in the fact that variou...
Xin Zhao, Sung Kyu Lim
PAM
2011
Springer
12 years 10 months ago
Peeling Away Timing Error in NetFlow Data
In this paper, we characterize, quantify, and correct timing errors introduced into network flow data by collection and export via Cisco NetFlow version 9. We find that while som...
Brian Trammell, Bernhard Tellenbach, Dominik Schat...
ASPDAC
2008
ACM
129views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Clock tree synthesis with data-path sensitivity matching
This paper investigates methods for minimizing the impact of process variation on clock skew using buffer and wire sizing. While most papers on clock trees ignore data-path circuit...
Matthew R. Guthaus, Dennis Sylvester, Richard B. B...
USS
2008
13 years 9 months ago
An Improved Clock-skew Measurement Technique for Revealing Hidden Services
The Tor anonymisation network allows services, such as web servers, to be operated under a pseudonym. In previous work Murdoch described a novel attack to reveal such hidden servi...
Sebastian Zander, Steven J. Murdoch
ASPDAC
2001
ACM
104views Hardware» more  ASPDAC 2001»
13 years 11 months ago
Optimal spacing and capacitance padding for general clock structures
Clock-tuning has been classified as important but tough tasks due to the non-convex nature caused by the skew requirements. As a result, all existing mathematical programming appr...
Yu-Min Lee, Hing Yin Lai, Charlie Chung-Ping Chen
CCS
2006
ACM
13 years 11 months ago
Hot or not: revealing hidden services by their clock skew
Location-hidden services, as offered by anonymity systems such as Tor, allow servers to be operated under a pseudonym. As Tor is an overlay network, servers hosting hidden service...
Steven J. Murdoch
DAC
2010
ACM
13 years 11 months ago
An efficient phase detector connection structure for the skew synchronization system
Clock skew optimization continues to be an important concern in circuit designs. To overcome the influence caused by PVT variations, the automatic skew synchronization scheme can ...
Yu-Chien Kao, Hsuan-Ming Chou, Kun-Ting Tsai, Shih...
DAC
2007
ACM
13 years 11 months ago
Effects of Coupling Capacitance and Inductance on Delay Uncertainty and Clock Skew
With the continuous increase of circuit density, interconnect length, and aspect ratio, the influence of capacitive and inductive coupling on timing characteristics of integrated ...
Abinash Roy, Noha H. Mahmoud, Masud H. Chowdhury
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
13 years 11 months ago
A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield
Abstract-- Nanometer VLSI systems demand robust clock distribution network design for increased process and operating condition variabilities. In this paper, we propose minimum clo...
Bao Liu, Andrew B. Kahng, Xu Xu, Jiang Hu, Ganesh ...
ICCAD
1993
IEEE
123views Hardware» more  ICCAD 1993»
13 years 11 months ago
Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line models
We have proposed an e cient measure to reduce the clock skew by assigning the clock network with variable branch widths. This measure has long been used for \H" clock tree. T...
Qing Zhu, Wayne Wei-Ming Dai, Joe G. Xi