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ASPDAC
2007
ACM
123views Hardware» more  ASPDAC 2007»
14 years 3 months ago
Coupling-aware Dummy Metal Insertion for Lithography
As integrated circuits manufacturing technology is advancing into 65nm and 45nm nodes, extensive resolution enhancement techniques (RETs) are needed to correctly manufacture a chip...
Liang Deng, Martin D. F. Wong, Kai-Yuan Chao, Hua ...
ISPD
1999
ACM
95views Hardware» more  ISPD 1999»
14 years 3 months ago
Incremental capacitance extraction and its application to iterative timing-driven detailed routing
In this paper, we consider delay optimization in multilayer detailed routing. Given a detailed routing by some detailed router, we iteratively improve the delays of critical nets ...
Yanhong Yuan, Prithviraj Banerjee
DAC
2000
ACM
14 years 3 months ago
TACO: timing analysis with coupling
: The impact of coupling capacitance on delay is usually estimated by scaling the coupling capacitances (often by a factor of 2) and modeling them as grounded. This simple approach...
Ravishankar Arunachalam, Karthik Rajagopal, Lawren...
ISPD
2005
ACM
205views Hardware» more  ISPD 2005»
14 years 4 months ago
Coupling aware timing optimization and antenna avoidance in layer assignment
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
Di Wu, Jiang Hu, Rabi N. Mahapatra
ISQED
2005
IEEE
81views Hardware» more  ISQED 2005»
14 years 4 months ago
Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer
Due to the rapid development of manufacturing process technology and tight marketing schedule, the chip design and manufacturing always work toward an integrated solution to achie...
Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong
ISQED
2006
IEEE
89views Hardware» more  ISQED 2006»
14 years 5 months ago
Study of Floating Fill Impact on Interconnect Capacitance
It is well known that fill insertion adversely affects total and coupling capacitance of interconnects. While grounded fill can be extracted by full-chip extractors, floating ...
Andrew B. Kahng, Kambiz Samadi, Puneet Sharma
ICCD
2004
IEEE
135views Hardware» more  ICCD 2004»
14 years 8 months ago
Design Methodologies and Architecture Solutions for High-Performance Interconnects
In Deep Sub-Micron (DSM) technologies, interconnects play a crucial role in the correct functionality and largely impact the performance of complex System-on-Chip (SoC) designs. F...
Davide Pandini, Cristiano Forzan, Livio Baldi