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DFT
2004
IEEE
93views VLSI» more  DFT 2004»
13 years 11 months ago
First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique
This paper presents a novel delay fault testing technique, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overh...
Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Rayc...
EURODAC
1994
IEEE
130views VHDL» more  EURODAC 1994»
13 years 11 months ago
RESIST: a recursive test pattern generation algorithm for path delay faults
This paper presents Resist, a recursive test pattern generation (TPG) algorithm for path delay fault testing of scan-based circuits. In contrast to other approaches, it exploits t...
Karl Fuchs, Michael Pabst, Torsten Rössel
DATE
1999
IEEE
91views Hardware» more  DATE 1999»
13 years 11 months ago
Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks
In this paper we show that the already known method of using multiplexers for making the inputs and outputs of the embedded blocks accessible by the primary ports of the Integrate...
Dimitris Nikolos, Haridimos T. Vergos, Th. Haniota...
ASYNC
2006
IEEE
92views Hardware» more  ASYNC 2006»
14 years 1 months ago
Low-Overhead Testing of Delay Faults in High-Speed Asynchronous Pipelines
We propose a low-overhead method for delay fault testing in high-speed asynchronous pipelines. The key features of our work are: (i) testing strategies can be administered using l...
Gennette Gill, Ankur Agiwal, Montek Singh, Feng Sh...
VTS
2008
IEEE
83views Hardware» more  VTS 2008»
14 years 1 months ago
LS-TDF: Low-Switching Transition Delay Fault Pattern Generation
— Higher chip densities and the push for higher performance have continued to drive design needs. Transition delay fault testing has become the preferred method for ensuring thes...
Jeremy Lee, Mohammad Tehranipoor
ICCAD
2003
IEEE
127views Hardware» more  ICCAD 2003»
14 years 4 months ago
Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage
Path delay fault testing becomes increasingly important due to higher clock rates and higher process variability caused by shrinking geometries. Achieving high-coverage path delay...
Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Pun...