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89

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DFT
1993
IEEE

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Layout Level Design for Testability Strategy Applied to a CMOS Cell Library

15 years 7 months ago

Layout Level Design for Testability Strategy Applied to a CMOS Cell Library

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M. Rullán, F. C. Blom, J. Oliver, C. Ferrer

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89

Voted

DFT
1993
IEEE

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High Level Synthesis Techniques for Efficient Built-In-Self Repair

15 years 7 months ago

High Level Synthesis Techniques for Efficient Built-In-Self Repair

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Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey

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115

Voted

DFT
1993
IEEE

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Neural Networks for Multiple Fault Diagnosis in Analog Circuits

15 years 7 months ago

Neural Networks for Multiple Fault Diagnosis in Analog Circuits

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Alessandra Fanni, Alessandro Giua, Enrico Sandoli

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