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DFT
2005
IEEE
102views VLSI» more  DFT 2005»
13 years 6 months ago
Using Statistical Transformations to Improve Compression for Linear Decompressors
Linear decompressors are the dominant methodology used in commercial test data compression tools. However, they are generally not able to exploit correlations in the test data, an...
Samuel I. Ward, Chris Schattauer, Nur A. Touba
DFT
2005
IEEE
132views VLSI» more  DFT 2005»
13 years 6 months ago
Low Power BIST Based on Scan Partitioning
A built-in self-test (BIST) scheme is presented which both reduces overhead for detecting random-pattern-resistant (r.p.r.) faults as well as reduces power consumption during test...
Jinkyu Lee, Nur A. Touba
DFT
2005
IEEE
88views VLSI» more  DFT 2005»
13 years 9 months ago
Efficient Exact Spare Allocation via Boolean Satisfiability
Fabricating large memory and processor arrays is subject to physical failures resulting in yield degradation. The strategy of incorporating spare rows and columns to obtain reason...
Fang Yu, Chung-Hung Tsai, Yao-Wen Huang, D. T. Lee...
DFT
2005
IEEE
83views VLSI» more  DFT 2005»
13 years 9 months ago
An ILP Formulation for Yield-driven Architectural Synthesis
Data flow graph dominant designs, such as communication video and audio applications, are common in today’s IC industry. In these designs, the datapath resources (e.g., adders,...
Zhaojun Wo, Israel Koren, Maciej J. Ciesielski
DFT
2005
IEEE
110views VLSI» more  DFT 2005»
13 years 9 months ago
A design flow for protecting FPGA-based systems against single event upsets
SRAM-based Field Programmable Gate Arrays (FPGAs) are very susceptible to Single Event Upsets (SEUs) that may have dramatic effects on the circuits they implement. In this paper w...
Luca Sterpone, Massimo Violante
DFT
2005
IEEE
92views VLSI» more  DFT 2005»
13 years 9 months ago
Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment
This paper presents a new test methodology which utilizes the Programming Language Interface (PLI) for performing fault simulation of combinational or full scan Intellectual Prope...
Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lom...
DFT
2005
IEEE
64views VLSI» more  DFT 2005»
13 years 9 months ago
Implementation of Concurrent Checking Circuits by Independent Sub-circuits
The present paper proposes a new method for detecting arbitrary faults in a functional circuit when the set of codewords is limited and known in advance. The method is based on im...
Vladimir Ostrovsky, Ilya Levin
DFT
2005
IEEE
81views VLSI» more  DFT 2005»
13 years 9 months ago
Modeling QCA Defects at Molecular-level in Combinational Circuits
This paper analyzes the deposition defects in devices and circuits made of Quantum-dot Cellular Automata (QCA) for molecular implementation. Differently from metal-based QCA, in ...
Mariam Momenzadeh, Marco Ottavi, Fabrizio Lombardi
DFT
2005
IEEE
200views VLSI» more  DFT 2005»
13 years 9 months ago
Data Dependent Jitter (DDJ) Characterization Methodology
A new jitter model is developed using Matlab and Spice to analyze Data Dependent Jitter (DDJ) in serial data integrated circuits. The simulation results show that DDJ is dependent...
Kyung Ki Kim, Yong-Bin Kim, Fabrizio Lombardi