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DSD
2003
IEEE
142views Hardware» more  DSD 2003»
13 years 11 months ago
FC-Min: A Fast Multi-Output Boolean Minimizer
We present a novel heuristic algorithm for two-level Boolean minimization. In contrast to the other approaches, the proposed method firstly finds the coverage of the on-sets and f...
Petr Fiser, Jan Hlavicka, Hana Kubatova
DSD
2003
IEEE
69views Hardware» more  DSD 2003»
13 years 11 months ago
A VLIW Architecture for Logarithmic Arithmetic
The Logarithmic Number System (LNS) is an alternative to IEEE-754 standard floating-point arithmetic. LNS multiply, divide and square root are easier than IEEE-754 and naturally ...
Mark G. Arnold
DSD
2003
IEEE
69views Hardware» more  DSD 2003»
13 years 11 months ago
A New Algorithm for High-Speed Projection in Point Rendering Applications
Margarita Amor, Montserrat Bóo, Ánge...
DSD
2003
IEEE
97views Hardware» more  DSD 2003»
13 years 11 months ago
A Quadruple Precision and Dual Double Precision Floating-Point Multiplier
Double precision floating-point arithmetic is inadequate for many scientific computations. This paper presents the design of a quadruple precision floating-point multiplier tha...
Ahmet Akkas, Michael J. Schulte