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    FPL
    2007
    Springer
    98views Hardware» more  FPL 2007»
    Module Graph Merging and Placement to Reduce Reconfiguration Overheads in Paged FPGA Devices
    14 years 10 months ago
    Module Graph Merging and Placement to Reduce Reconfiguration Overheads in Paged FPGA Devices
    Download  www.cse.unsw.edu.au
    Reconfiguration time in dynamically-reconfigurable modular systems can severely limit application run-time compared to the critical path delay. In this paper we present a novel ...
    Shannon Koh, Oliver Diessel
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