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115
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MICRO
2009
IEEE
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MICRO 2009
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Adaptive line placement with the set balancing cache
15 years 10 months ago
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Efficient memory hierarchy design is critical due to the increasing gap between the speed of the processors and the memory. One of the sources of inefficiency in current caches is...
Dyer Rolán, Basilio B. Fraguela, Ramon Doal...
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