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    DFT
    2003
    IEEE
    117views VLSI» more  DFT 2003»
    Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code
    15 years 2 months ago
    Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code
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    We describe a method for designing fault tolerant circuits based on an extension of a Concurrent Error Detection (CED) technique. The proposed extension combines parity check code...
    Sobeeh Almukhaizim, Yiorgos Makris
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