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110
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DFT
2009
IEEE
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VLSI
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DFT 2009
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Reduced Precision Checking for a Floating Point Adder
15 years 6 months ago
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We present an error detection technique for a floating point adder which uses a checker adder of reduced precision to determine if the result is correct within some error bound. O...
Patrick J. Eibl, Andrew D. Cook, Daniel J. Sorin
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