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EURODAC
1995
IEEE
195views VHDL» more  EURODAC 1995»
15 years 11 days ago
A hardware/software partitioning algorithm for pipelined instruction set processor
This paper proposes a new method to design an optimal instruction set for pipelined ASIP development using a formal HW/SW codesign methodology. The codesign task addressed in this...
Binh Ngoc Nguyen, Masaharu Imai, Nobuyuki Hikichi