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DSD
2011
IEEE
200views Hardware» more  DSD 2011»
12 years 6 months ago
Microthreading as a Novel Method for Close Coupling of Custom Hardware Accelerators to SVP Processors
Abstract—We present a new low-level interfacing scheme for connecting custom accelerators to processors that tolerates latencies that usually occur when accessing hardware accele...
Jaroslav Sykora, Leos Kafka, Martin Danek, Lukas K...
ICASSP
2011
IEEE
12 years 10 months ago
FPGA implementation made easy for applied digital signal processing courses
Applied digital signal processing courses offered at many universities do not normally include FPGA implementation of signal processing algorithms. This is due to the fact that st...
Nasser D. Kehtarnavaz, Sidharth Mahotra
ICASSP
2011
IEEE
12 years 10 months ago
High-throughput implementation of tree-search algorithms for vector precoding
This contribution analyzes the architecture design and FPGA implementation of high-throughput multiuser vector precoders. The most complex task of such precoders, i.e. the search ...
Maitane Barrenechea, Luis G. Barbero, Idoia Jimene...
LATINCRYPT
2010
13 years 4 months ago
Accelerating Lattice Reduction with FPGAs
We describe an FPGA accelerator for the Kannan–Fincke– Pohst enumeration algorithm (KFP) solving the Shortest Lattice Vector Problem (SVP). This is the first FPGA implementati...
Jérémie Detrey, Guillaume Hanrot, Xa...
AIA
2006
13 years 7 months ago
FPGA-Targeted Neural Architecture for Embedded Alertness Detection
Several recent works have used neural networks to discriminate vigilance states in humans from electroencephalographic (EEG) signals. Our study aims at being more exhaustive. It t...
Bernard Girau, Khaled Ben Khalifa
FPL
2004
Springer
143views Hardware» more  FPL 2004»
13 years 10 months ago
Exploring Area/Delay Tradeoffs in an AES FPGA Implementation
Abstract. Field-Programmable Gate Arrays (FPGAs) have lately become a popular target for implementing cryptographic block ciphers, as a well-designed FPGA solution can combine some...
Joseph Zambreno, David Nguyen, Alok N. Choudhary
FPL
2009
Springer
166views Hardware» more  FPL 2009»
13 years 11 months ago
Modeling post-techmapping and post-clustering FPGA circuit depth
This paper presents an analytical model that relates FPGA architectural parameters to the expected speed of FPGA implementation. More precisely, the model relates the lookuptable ...
Joydip Das, Steven J. E. Wilton, Philip Heng Wai L...
FCCM
2005
IEEE
96views VLSI» more  FCCM 2005»
14 years 3 days ago
FPGA-Based CDMA Switch for Networks-on-Chip
This paper presents timing and area results for an FPGA implementation of a CDMA-based switch for networkson-chip. The design was mapped onto the Xilinx Virtex4 XC4VLX200 device u...
Daewook Kim, Manho Kim, Gerald E. Sobelman
FCCM
2009
IEEE
165views VLSI» more  FCCM 2009»
14 years 1 months ago
Accelerating Quadrature Methods for Option Valuation
This paper presents an architecture for FPGA acceleration of quadrature methods used for pricing complex options, such as discrete barrier, Bermudan, and American options. The arc...
Anson H. T. Tse, David B. Thomas, Wayne Luk
ARC
2009
Springer
241views Hardware» more  ARC 2009»
14 years 1 months ago
Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm
As the need for information security increases in our everyday life, the job of encoding/decoding for secure information delivery becomes a critical issue in data network systems. ...
Jaeyoung Yi, Karam Park, Joonseok Park, Won Woo Ro