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CF
2007
ACM
13 years 8 months ago
Accelerating memory decryption and authentication with frequent value prediction
This paper presents a novel architectural technique to hide fetch latency overhead of hardware encrypted and authenticated memory. A number of recent secure processor designs have...
Weidong Shi, Hsien-Hsin S. Lee
ASPLOS
2000
ACM
13 years 8 months ago
Frequent Value Locality and Value-Centric Data Cache Design
By studying the behavior of programs in the SPECint95 suite we observed that six out of eight programs exhibit a new kind of value locality, the frequent value locality, according...
Youtao Zhang, Jun Yang 0002, Rajiv Gupta
HIPC
2003
Springer
13 years 9 months ago
FV-MSB: A Scheme for Reducing Transition Activity on Data Buses
Power consumption becomes an important issue for modern processors. The off-chip buses consume considerable amount of total power [9,7]. One effective way to reduce power is to red...
Dinesh C. Suresh, Jun Yang 0002, Chuanjun Zhang, B...
ACISICIS
2005
IEEE
13 years 9 months ago
An Effective Cache Overlapping Storage Structure for SMT Processors
Simultaneous Multithreaded (SMT) processors improve the instruction throughput by allowing fetching and running instructions from several threads simultaneously at a single cycle....
Liqiang He, Zhiyong Liu