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    SIPS
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    IEEE
    148views Signal Processing» more  SIPS 2007»
    An Area-Efficient FPGA-Based Architecture for Fully-Parallel Stochastic LDPC Decoding
    15 years 3 months ago
    An Area-Efficient FPGA-Based Architecture for Fully-Parallel Stochastic LDPC Decoding
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    Stochastic decoding is a new alternative method for low complexity decoding of error-correcting codes. This paper presents the first hardware architecture for stochastic decoding...
    Saeed Sharifi Tehrani, Shie Mannor, Warren J. Gros...
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