Sciweavers

TVLSI
2010
13 years 1 months ago
On the Power Management of Simultaneous Multithreading Processors
SMT processors are widely used in high performance computing tasks. However, with the improved performance of the SMT architecture, the utilization of their functional units is sig...
Ahmed Youssef, Mohamed Zahran, Mohab Anis, Mohamed...
ICCAD
2009
IEEE
118views Hardware» more  ICCAD 2009»
13 years 4 months ago
Memory organization and data layout for instruction set extensions with architecturally visible storage
Present application specific embedded systems tend to choose instruction set extensions (ISEs) based on limitations imposed by the available data bandwidth to custom functional un...
Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leb...
GLVLSI
2010
IEEE
168views VLSI» more  GLVLSI 2010»
13 years 6 months ago
A revisit to voltage partitioning problem
We revisit voltage partitioning problem when the mapped voltages of functional units are predetermined. If energy consumption is estimated by formulation E = CV 2 , a published wo...
Tao Lin, Sheqin Dong, Bei Yu, Song Chen, Satoshi G...
PDPTA
2000
13 years 7 months ago
The KIT COSMOS Processor: Introducing CONDOR
Abstract In this paper, we propose a microprocessor architecture which eciently utilizes nextgeneration semiconductor technology. While the technology makes it possible to integrat...
Toshinori Sato, Itsujiro Arita
ASPDAC
2008
ACM
87views Hardware» more  ASPDAC 2008»
13 years 8 months ago
An efficient performance improvement method utilizing specialized functional units in Behavioral Synthesis
This paper proposes a novel Behavioral Synthesis method that improves performance of synthesized circuits utilizing specialized functional units effectively. Specialized functional...
Tsuyoshi Sadakata, Yusuke Matsunaga
ISSS
1995
IEEE
117views Hardware» more  ISSS 1995»
13 years 9 months ago
Scheduling and resource binding for low power
Decisions taken at the earliest steps of the design process may have a significantimpact on the characteristics of the final implementation. This paper illustrates how power con...
Enric Musoll, Jordi Cortadella
FPL
2006
Springer
95views Hardware» more  FPL 2006»
13 years 10 months ago
A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor
This paper presents a reconfigurable functional unit (RFU) for an adaptive dynamic extensible processor. The processor can tune its extended instructions to the target application...
Hamid Noori, Farhad Mehdipour, Kazuaki Murakami, K...
EMSOFT
2006
Springer
13 years 10 months ago
Compiler-assisted leakage energy optimization for clustered VLIW architectures
Miniaturization of devices and the ensuing decrease in the threshold voltage has led to a substantial increase in the leakage component of the total processor energy consumption. ...
Rahul Nagpal, Y. N. Srikant
APCSAC
2004
IEEE
13 years 10 months ago
Dynamic Reallocation of Functional Units in Superscalar Processors
In the context of general-purpose processing, an increasing number of diverse functional units are added to cover a wide spectrum of applications. However, it is still possible to ...
Marc Epalza, Paolo Ienne, Daniel Mlynek
CONPAR
1992
13 years 10 months ago
Asynchronous Polycyclic Architecture
The Asynchronous Polycyclic Architecture (APA) is a new processor design for numerically intensive applications. APA resembles the VLIW architecture, in that it provides independen...
Geraldo Lino de Campos