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GLVLSI
2000
IEEE
105views VLSI» more  GLVLSI 2000»
13 years 10 months ago
An evolutionary approach to timing driven FPGA placement
: We propose a novel evolutionary approach to the problem of timing-driven FPGA placement. The method used is evolutionary programming (EP) with incremental position encoded in the...
R. Venkatraman, Lalit M. Patnaik
GLVLSI
2000
IEEE
116views VLSI» more  GLVLSI 2000»
13 years 10 months ago
Reducing bus transition activity by limited weight coding with codeword slimming
Transitions on high capacitance busses in VLSI systems result in considerable power dissipation. Various coding schemes have been proposed in literature to encode the input signal...
Vijay Sundararajan, Keshab K. Parhi
GLVLSI
2000
IEEE
82views VLSI» more  GLVLSI 2000»
13 years 10 months ago
Transparent repeaters
Radu M. Secareanu, Eby G. Friedman
GLVLSI
2000
IEEE
83views VLSI» more  GLVLSI 2000»
13 years 10 months ago
Formal hardware verification by integrating HOL and MDG
V. K. Pisini, Sofiène Tahar, Paul Curzon, O...
GLVLSI
2000
IEEE
104views VLSI» more  GLVLSI 2000»
13 years 10 months ago
A new technique for estimating lower bounds on latency for high level synthesis
In this paper we present a novel and fast estimation technique that produces tight latency lower bounds for Data Flow Graphs representing time critical segments of the application...
Helvio P. Peixoto, Margarida F. Jacome
GLVLSI
2000
IEEE
87views VLSI» more  GLVLSI 2000»
13 years 10 months ago
Speeding up symbolic model checking by accelerating dynamic variable reordering
Symbolic Model checking is a widely used technique in sequential verification. As the size of the OBDDs and also the computation time depends on the order of the input variables,...
Christoph Meinel, Christian Stangier
GLVLSI
2000
IEEE
113views VLSI» more  GLVLSI 2000»
13 years 10 months ago
A novel technique for sea of gates global routing
We present a novel global routing and cross-point assignment methodology for sea-of-gates (SOG) designs. Using the proposed congestion driven spanning trees (CDST), and continuous...
Bharat Krishna, C. Y. Roger Chen, Naresh Sehgal
GLVLSI
2000
IEEE
145views VLSI» more  GLVLSI 2000»
13 years 10 months ago
Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures
Circuit interconnect has become a substantial obstacle in the design of high performance systems. In this paper we explore a new routing paradigm that strikes at the root of the i...
Cheng-Kok Koh, Patrick H. Madden
GLVLSI
2000
IEEE
90views VLSI» more  GLVLSI 2000»
13 years 10 months ago
Low power high speed analog-to-digital converter for wireless communications
A new ADC architecture is devised. This architecture is memory based, in which the last sample is used to predict the current one, resulting in both power dissipation and energy r...
A. E. Hussein, Mohamed I. Elmasry