Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chi...
Pramod Subramanyan, Virendra Singh, Kewal K. Saluj...
We revisit voltage partitioning problem when the mapped voltages of functional units are predetermined. If energy consumption is estimated by formulation E = CV 2 , a published wo...
Tao Lin, Sheqin Dong, Bei Yu, Song Chen, Satoshi G...
The paper presents a novel high-level power modeling and estimation framework. The approach is based on a synergic integration of aspect-oriented programming(AOP) and SystemC. Mac...
Loop caches provide an effective method for decreasing memory hierarchy energy consumption by storing frequently executed code in a more energy efficient structure than the level ...
As the rated performance of microprocessors increases, voltage droop emergencies become a significant problem. In this paper, two new techniques to combat voltage droop emergencie...
Jia Zhao, Basab Datta, Wayne P. Burleson, Russell ...
In this paper, we present an approved linear-time algorithm for statistical leakage analysis in the present of any spatial correlation condition (strong or weak). The new algorith...
For timing-driven or yield-driven designs, non-tree routing has become more and more popular and additional loops provide the redundant paths to protect against the effect of the ...
This paper describes a physics-based semi-analytical model for Schottky-barrier carbon nanotube (CNT) and graphene nanoribbon (GNR) transistors. The model includes the treatment o...
Xuebei Yang, Gianluca Fiori, Giuseppe Iannaccone, ...
Transistor aging effects (NBTI and PBTI) impact the reliability of SRAM in nano-scale CMOS technologies. In this research, the combined effect of NBTI and PBTI on power gated SRAM...
The electromagnetic interaction of on-chip antennas and metal interconnects modeled in a 250 nm complementary metal-oxide semiconductor (CMOS) technology is investigated. A finite...