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123
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DATE
2005
IEEE
121
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Hardware
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DATE 2005
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Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization
15 years 9 months ago
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hal.archives-ouvertes.fr
— This paper suggests a methodology to decrease the power of a static CMOS standard cell design at layout level by focusing on switched capacitance. The term switched is the key:...
Paul Zuber, Armin Windschiegl, Raúl Medina ...
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