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ITC
2003
IEEE
148views Hardware» more  ITC 2003»
15 years 10 months ago
Linearity Testing of Precision Analog-to-Digital Converters Using Stationary Nonlinear Inputs
As the performance of Analog-to-Digital Converters continues to improve, it is becoming more challenging and costly to develop sufficiently fast and low-drift signal generators th...
Le Jin, Kumar L. Parthasarathy, Turker Kuyel, Dega...
ITC
2003
IEEE
134views Hardware» more  ITC 2003»
15 years 10 months ago
Effectiveness Improvement of ECR Tests
Energy Consumption Ratio (ECR) test, a current-based test, has shown its ability to reduce the impact of process variations and detect hard-to-detect faults. The effectiveness of ...
Wanli Jiang, Erik Peterson, Bob Robotka
ITC
2003
IEEE
136views Hardware» more  ITC 2003»
15 years 10 months ago
A BIST Solution for The Test of I/O Speed
A delay-locked loop (DLL) based built-in self test (BIST) circuit has been designed with a 0.18 µ m TSMC process (CM018) to test chip I/O speeds, specifically, the setup and hold...
Cheng Jia, Linda S. Milor
ITC
2003
IEEE
222views Hardware» more  ITC 2003»
15 years 10 months ago
Race: A Word-Level ATPG-Based Constraints Solver System For Smart Random Simulation
Functional verification of complex designs largely relies on the use of simulation in conjunction high-level verification languages (HVL) and test-bench automation (TBA) tools. In...
Mahesh A. Iyer
ITC
2003
IEEE
114views Hardware» more  ITC 2003»
15 years 10 months ago
Test-Based Model Generation For Legacy Systems
We study the extension of applicability of system-level testing techniques to the construction of a consistent model of (legacy) systems under test, which are seen as black boxes....
Hardi Hungar, Tiziana Margaria, Bernhard Steffen
112
Voted
ITC
2003
IEEE
112views Hardware» more  ITC 2003»
15 years 10 months ago
Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault
Intermittent scan chain hold-time fault is discussed in this paper and a method to diagnose the faulty site in a scan chain is proposed as well. Unlike the previous scan chain dia...
Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Cheng-...
ITC
2003
IEEE
116views Hardware» more  ITC 2003»
15 years 10 months ago
Circular BIST testing the digital logic within a high speed Serdes
High Speed Serializer Deserializers (serdes) are traditionally tested using functional BIST. This paper presents an improved BIST for testing the digital part of a serdes using ci...
Graham Hetherington, Richard Simpson
ITC
2003
IEEE
93views Hardware» more  ITC 2003»
15 years 10 months ago
Hybrid Multisite Testing at Manufacturing
This paper deals with Hybrid multisite testing of VLSI chips by utilizing automatic test equipment (ATE) in connection with built-in self-test (BIST). The performance of a multisi...
Hamidreza Hashempour, Fred J. Meyer, Fabrizio Lomb...
ITC
2003
IEEE
135views Hardware» more  ITC 2003»
15 years 10 months ago
VDD Ramp Testing for RF Circuits
José Pineda de Gyvez, Guido Gronthoud, Rash...
ITC
2003
IEEE
120views Hardware» more  ITC 2003»
15 years 10 months ago
High Quality ATPG for Delay Defects
: The paper presents a novel technique for generating effective vectors for delay defects. The test set achieves high path delay fault coverage to capture smalldistributed delay de...
Puneet Gupta, Michael S. Hsiao