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126
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DATE
2004
IEEE
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Hardware
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DATE 2004
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Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks
15 years 6 months ago
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www.nd.edu
Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures ...
Zhong Wang, Xiaobo Sharon Hu
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