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    GLVLSI
    2007
    IEEE
    151views VLSI» more  GLVLSI 2007»
    Hand-in-hand verification of high-level synthesis
    15 years 21 days ago
    Hand-in-hand verification of high-level synthesis
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    This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...
    Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Ma...
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