Sciweavers

HPCA
1996
IEEE
13 years 10 months ago
Telegraphos: High-Performance Networking for Parallel Processing on Workstation Clusters
Networks of workstations and high-performance microcomputers have been rarely used for running highperformance applicationslike multimedia, simulations,scientific and engineering ...
Evangelos P. Markatos, Manolis Katevenis
HPCA
1996
IEEE
13 years 10 months ago
Improving Release-Consistent Shared Virtual Memory Using Automatic Update
Shared virtual memory is a software technique to provide shared memory on a network of computers without special hardware support. Although several relaxed consistency models and ...
Liviu Iftode, Cezary Dubnicki, Edward W. Felten, K...
HPCA
1996
IEEE
13 years 10 months ago
Fault-Tolerance with Multimodule Routers
The current multiprocessors such asCray T3D support interprocessor communication using partitioned dimension-order routers (PDRs). In a PDR implementation, the routing logic and sw...
Suresh Chalasani, Rajendra V. Boppana
HPCA
1996
IEEE
13 years 10 months ago
Predictive Sequential Associative Cache
In this paper, we propose a cache design that provides the same miss rate as a two-way set associative cache, but with a access time closer to a direct-mapped cache. As with other...
Brad Calder, Dirk Grunwald, Joel S. Emer
HPCA
1996
IEEE
13 years 10 months ago
Co-Scheduling Hardware and Software Pipelines
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded process...
Ramaswamy Govindarajan, Erik R. Altman, Guang R. G...
HPCA
1996
IEEE
13 years 10 months ago
Protected, User-Level DMA for the SHRIMP Network Interface
Traditional DMA requires the operating system to perform many tasks to initiate a transfer, with overhead on the order of hundreds or thousands of CPU instructions. This paper des...
Matthias A. Blumrich, Cezary Dubnicki, Edward W. F...
HPCA
1996
IEEE
13 years 10 months ago
Register File Design Considerations in Dynamically Scheduled Processors
We have investigated the register file requirements of dynamically scheduled processors using register renaming and dispatch queues running the SPEC92 benchmarks. We looked at pro...
Keith I. Farkas, Norman P. Jouppi, Paul Chow
HPCA
1996
IEEE
13 years 10 months ago
A Comparison of Entry Consistency and Lazy Release Consistency Implementations
This paper compares several implementations of entry consistency (EC) and lazy release consistency (LRC), two relaxed memory models in use with software distributed shared memory ...
Sarita V. Adve, Alan L. Cox, Sandhya Dwarkadas, Ra...