HPCA
2008
IEEE
14 years 6 months ago
2008
IEEE
Hard-to-predict branches depending on longlatency cache-misses have been recognized as a major performance obstacle for modern microprocessors. With the widening speed gap between...
HPCA
2008
IEEE
14 years 6 months ago
2008
IEEE
Interconnection networks-on-chip (NOCs) are rapidly replacing other forms of interconnect in chip multiprocessors and system-on-chip designs. Existing interconnection networks use...
HPCA
2008
IEEE
14 years 6 months ago
2008
IEEE
Simultaneous Multithreading (SMT) attempts to keep a dynamically scheduled processor's resources busy with work from multiple independent threads. Threads with longlatency st...
HPCA
2008
IEEE
14 years 6 months ago
2008
IEEE
Dynamic binary translation (DBT) is a runtime instrumentation technique commonly used to support profiling, optimization, secure execution, and bug detection tools for application...
HPCA
2008
IEEE
14 years 6 months ago
2008
IEEE
This paper describes a comprehensive approach for using the memory controller to improve DRAM energy efficiency and manage DRAM power. We make three contributions: (1) we describe...
HPCA
2008
IEEE
14 years 6 months ago
2008
IEEE
Power consumption within the disk-based storage subsystem forms a substantial portion of the overall energy footprint in commodity systems. Researchers have proposed external cach...
HPCA
2008
IEEE
14 years 6 months ago
2008
IEEE
Estimating the maximum power and thermal characteristics of a processor is essential for designing its power delivery system, packaging, cooling, and power/thermal management sche...
HPCA
2008
IEEE
14 years 6 months ago
2008
IEEE
HPCA
2008
IEEE
14 years 6 months ago
2008
IEEE
HPCA
2008
IEEE
14 years 6 months ago
2008
IEEE
Power-Efficient DRAM Speculation (PEDS) is a power optimization targeted at broadcast-based sharedmemory multiprocessor systems that speculatively access DRAM in parallel with the...