Sciweavers

ICPP
1996
IEEE
13 years 11 months ago
A Timestamp-based Selective Invalidation Scheme for Multiprocessor Cache Coherence
- Among all software cache coherence strategaes, the ones that are based on the concept of tamestamps show the greatest potentaal an terms of cache performance. The early tamestamp...
Xin Yuan, Rami G. Melhem, Rajiv Gupta
ICPP
1996
IEEE
13 years 11 months ago
Polynomial-Time Nested Loop Fusion with Full Parallelism
Data locality and synchronization overhead are two important factors that affect the performance of applications on multiprocessors. Loop fusion is an effective way for reducing s...
Edwin Hsing-Mean Sha, Chenhua Lang, Nelson L. Pass...
ICPP
1996
IEEE
13 years 11 months ago
Parallel Implementation of Cone Beam Tomography
Abstract - Three dimensional computed tomography is a computationally intensive procedure, requiring large amounts of R A M and processing power. Parallel methods for two dimension...
David A. Reimann, Vipin Chaudhary, Michael J. Flyn...
ICPP
1996
IEEE
13 years 11 months ago
On the Scalability of 2-D Wavelet Transform Algorithms on Fine-grained Parallel Machines
: We study the scalability of 2-D discrete wavelet transform algorithms on fine-grained parallel architectures. The principal operation in the 2-D DWT is the filtering operation us...
Jamshed N. Patel, Ashfaq A. Khokhar, Leah H. Jamie...
ICPP
1996
IEEE
13 years 11 months ago
Scheduling of Wavefront Parallelism on Scalable Shared-memory Multiprocessors
Tiling exploits temporal reuse carried by an outer loop of a loop nest to enhance cache locality. Loop skewing is typically required to make tiling legal. This restricts parallelis...
Naraig Manjikian, Tarek S. Abdelrahman
ICPP
1996
IEEE
13 years 11 months ago
Mechanisms for Mapping High-Level Parallel Performance Data
A primary problem in the performance measurement of high-level parallel programming languages is to map lowlevel events to high-level programming constructs. We discuss several as...
R. Bruce Irvin, Barton P. Miller