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83
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ISCAS
2006
IEEE
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ISCAS 2006
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A low-power clock frequency multiplier
15 years 8 months ago
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www.cacs.louisiana.edu
A low-power output feedback controlled frequency synthesizer. Our proposed circuit can be used for low-power multiplier is proposed for Delay Locked Loop (DLL) based application an...
Md. Ibrahim Faisal, Magdy A. Bayoumi, Peiyi Zhao
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