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127
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IESS
2007
Springer
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IESS 2007
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Error Containment in the Time-Triggered System-On-a-Chip Architecture
15 years 9 months ago
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www.vmars.tuwien.ac.at
Abstract: The time-triggered System-on-a-Chip (SoC) architecture provides a generic multicore system platform for a family of composable and dependable giga-scale SoCs. It supports...
Roman Obermaisser, Hermann Kopetz, Christian El Sa...
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