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ISCA
2010
IEEE
188views Hardware» more  ISCA 2010»
13 years 9 months ago
Guest Editor's Note
Dunren Che
ISCA
2010
IEEE
229views Hardware» more  ISCA 2010»
13 years 10 months ago
Understanding sources of inefficiency in general-purpose chips
Due to their high volume, general-purpose processors, and now chip multiprocessors (CMPs), are much more cost effective than ASICs, but lag significantly in terms of performance a...
Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Az...
ISCA
2010
IEEE
216views Hardware» more  ISCA 2010»
13 years 10 months ago
The impact of management operations on the virtualized datacenter
Virtualization has the potential to dramatically reduce the total cost of ownership of datacenters and increase the flexibility of deployments for general-purpose workloads. If pr...
Vijayaraghavan Soundararajan, Jennifer M. Anderson
ISCA
2010
IEEE
237views Hardware» more  ISCA 2010»
13 years 10 months ago
High performance cache replacement using re-reference interval prediction (RRIP)
Practical cache replacement policies attempt to emulate optimal replacement by predicting the re-reference interval of a cache block. The commonly used LRU replacement policy alwa...
Aamer Jaleel, Kevin B. Theobald, Simon C. Steely J...
ISCA
2010
IEEE
232views Hardware» more  ISCA 2010»
13 years 10 months ago
Evolution of thread-level parallelism in desktop applications
As the effective limits of frequency and instruction level parallelism have been reached, the strategy of microprocessor vendors has changed to increase the number of processing ...
Geoffrey Blake, Ronald G. Dreslinski, Trevor N. Mu...
ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
14 years 2 months ago
Translation caching: skip, don't walk (the page table)
This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page t...
Thomas W. Barr, Alan L. Cox, Scott Rixner
ISCA
2010
IEEE
222views Hardware» more  ISCA 2010»
14 years 2 months ago
Cohesion: a hybrid memory model for accelerators
Two broad classes of memory models are available today: models with hardware cache coherence, used in conventional chip multiprocessors, and models that rely upon software to mana...
John H. Kelm, Daniel R. Johnson, William Tuohy, St...
ISCA
2010
IEEE
247views Hardware» more  ISCA 2010»
14 years 3 months ago
An integrated GPU power and performance model
GPU architectures are increasingly important in the multi-core era due to their high number of parallel processors. Performance optimization for multi-core processors has been a c...
Sunpyo Hong, Hyesoon Kim
ISCA
2010
IEEE
231views Hardware» more  ISCA 2010»
14 years 4 months ago
The rebirth of neural networks
Olivier Temam
ISCA
2010
IEEE
199views Hardware» more  ISCA 2010»
14 years 4 months ago
Use ECP, not ECC, for hard failures in resistive memories
As leakage and other charge storage limitations begin to impair the scalability of DRAM, non-volatile resistive memories are being developed as a potential replacement. Unfortunat...
Stuart E. Schechter, Gabriel H. Loh, Karin Straus,...