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ISQED
2003
IEEE
86views Hardware» more  ISQED 2003»
14 years 25 days ago
Electrical and Thermal Analysis for System-in-a-Package (SiP) Implementation Platform
This paper presents an electrical and thermal performance analysis of System-in-a-Package (SiP) memory/logic implementation platform based on ChipLaminate-Chip (CLC) technology. I...
Michael X. Wang, Katsuharu Suzuki, Wayne Wei-Ming ...
ISQED
2003
IEEE
133views Hardware» more  ISQED 2003»
14 years 25 days ago
Impact of Interconnect Pattern Density Information on a 90nm Technology ASIC Design Flow
The importance of an interconnect pattern density model in ASIC design flow for a 90nm technology is presented. It is shown that performing the timing analysis at the worst-case c...
Payman Zarkesh-Ha, S. Lakshminarayann, Ken Doniger...
ISQED
2003
IEEE
78views Hardware» more  ISQED 2003»
14 years 25 days ago
An Embedded IDDQ Testing Architecture and Technique
In this paper an embedded IDDQ testing architecture is presented that targets to overcome the excessive hardware overhead requirements in built-in current sensing based testing ap...
Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni
ISQED
2003
IEEE
102views Hardware» more  ISQED 2003»
14 years 25 days ago
Modeling Crosstalk Induced Delay
The amplitude of coupled noise is often used in estimating the crosstalk effect. Coupling noise-induced delay measures the impact of crosstalk on circuit performance. Efficient c...
Chung-Kuan Tsai, Malgorzata Marek-Sadowska
ISQED
2003
IEEE
133views Hardware» more  ISQED 2003»
14 years 25 days ago
Analyzing Internal-Switching Induced Simultaneous Switching Noise
The internal-switching induced simultaneous switching noise (SSN) is studied in the paper. Unlike ground bounce caused by driving off-chip loading, both power-rail and ground-rail...
Li Yang, J. S. Yuan
ISQED
2003
IEEE
104views Hardware» more  ISQED 2003»
14 years 25 days ago
Elimination of false aggressors using the functional relationship for full-chip crosstalk analysis
As the portion of coupling capacitance increases in smaller process geometries, accurate coupled noise analysis is becoming more important in current design methodologies. We prop...
Jae-Seok Yang, Jeong-Yeol Kim, Joon-Ho Choi, Moon-...
ISQED
2003
IEEE
87views Hardware» more  ISQED 2003»
14 years 25 days ago
Coupled Simulation of Circuit and Piezoelectric Laminates
In this paper, an algorithm for the coupled simulation of circuit and piezoelectric laminate devices is presented. A finite element solver for piezoelectric laminates is included ...
Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram
ISQED
2003
IEEE
104views Hardware» more  ISQED 2003»
14 years 25 days ago
On-Chip Interconnect Inductance - Friend or Foe (Invited)
Inductance associated with on-chip wires can no longer be ignored as chip operation frequencies increase into GHz regime. Because the magnetic field propagates a very long range, ...
S. Simon Wong, C. Patrick Yue, Richard Chang, So-Y...
ISQED
2003
IEEE
644views Hardware» more  ISQED 2003»
14 years 25 days ago
Procedural Analog Design (PAD) Tool
Danica Stefanovic, Maher Kayal, Marc Pastre, Vanco...
ISQED
2003
IEEE
85views Hardware» more  ISQED 2003»
14 years 25 days ago
PDL: A New Physical Synthesis Methodology
In this paper, we propose a new physical synthesis methodology, PDL, which relaxes the timing constraints to obtain best optimality in terms of layout quality and timing quality. ...
Toshiyuki Shibuya, Rajeev Murgai, Tadashi Konno, K...