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108
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ASPDAC
2006
ACM
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ASPDAC 2006
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Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops
15 years 9 months ago
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cc.ee.ntu.edu.tw
Statistical timing analysis has been widely applied to predict the timing yield of VLSI circuits when process variations become significant. Existing statistical latch timing met...
Lizheng Zhang, Jeng-Liang Tsai, Weijen Chen, Yuhen...
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