Sciweavers

JSA
2000
103views more  JSA 2000»
13 years 3 months ago
Testing and built-in self-test - A survey
As the density of VLSI circuits increases it becomes attractive to integrate dedicated test logic on a chip. This Built-in Self-Test (BIST) approach not only offers economic benef...
Andreas Steininger
JSA
2000
175views more  JSA 2000»
13 years 3 months ago
Complete worst-case execution time analysis of straight-line hard real-time programs
In this article, the problem of finding a tight estimate on the worst-case execution time (WCET) of a real-time program is addressed. The analysis is focused on straight-line code...
Friedhelm Stappert, Peter Altenbernd
JSA
2000
90views more  JSA 2000»
13 years 3 months ago
An efficient implementation of tree-based multicast routing for distributed shared-memory multiprocessors
This paper presents an efficient routing and flow control mechanism to implement multidestination message passing in wormhole networks.It is targeted to situations where the size ...
Manuel P. Malumbres, José Duato
JSA
2000
116views more  JSA 2000»
13 years 3 months ago
Distributed vector architectures
Integrating processors and main memory is a promising approach to increase system performance. Such integration provides very high memory bandwidth that can be exploited efficientl...
Stefanos Kaxiras
JSA
2000
96views more  JSA 2000»
13 years 3 months ago
Design techniques for low-power systems
Portable products are being used increasingly. Because these systems are battery powered, reducing power consumption is vital. In this report we give the properties of low power d...
Paul J. M. Havinga, Gerard J. M. Smit
JSA
2000
115views more  JSA 2000»
13 years 3 months ago
Scheduling optimization through iterative refinement
Scheduling DAGs with communication times is the theoretical basis for achieving efficient parallelism on distributed memory systems. We generalize Graham's task-level in a ma...
Mayez A. Al-Mouhamed, Adel Al-Massarani
JSA
2000
103views more  JSA 2000»
13 years 3 months ago
O(n) routing in rearrangeable networks
In (2n)1)-stage rearrangeable networks, the routing time for any arbitrary permutation is X(n2 ) compared to its propagation delay O(n) only. Here, we attempt to identify the sets...
Nabanita Das, Krishnendu Mukhopadhyaya, Jayasree D...
JSA
2000
116views more  JSA 2000»
13 years 3 months ago
A fault tolerant routing algorithm based on cube algebra for hypercube systems
We propose an approach to determine the shortest path between the source and the destination nodes in a faulty or a nonfaulty hypercube. The number of faulty nodes and links may b...
Novruz M. Allahverdi, Sirzad S. Kahramanli, Kayhan...