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117
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ICCAD
2006
IEEE
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ICCAD 2006
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Soft error reduction in combinational logic using gate resizing and flipflop selection
15 years 11 months ago
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www.cecs.uci.edu
Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SE...
Rajeev R. Rao, David Blaauw, Dennis Sylvester
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