Sciweavers

    ISCAS
    2005
    IEEE
    126views Hardware» more  ISCAS 2005»
    Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation
    15 years 8 months ago
    Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation
    Download  koasas.kaist.ac.kr
    — The fully parallel LDPC decoding architecture can achieve high decoding throughput, but it suffers from large hardware complexity caused by a large set of processing units and ...
    In-Cheol Park, Se-Hyeon Kang
    claim paper
    Read More »
    Explore & Download
    Proceedings Preprints Top 5 Ranked Papers Publications Books Software Tutorials Presentations Lectures Notes Datasets
    Productivity Tools
    i2PDF i2Img i2Text i2OCR i2Symbol i2Type i2Speak i2Style i2Arabic i2Bopomo Latex Equation Editor
    Sciweavers
    About Community Cookies Privacy Policy Terms of Use

    Copyright © Sciweavers LLC, 2009-2026, USA.