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ASPDAC
2010
ACM
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ASPDAC 2010
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Statistical timing verification for transparently latched circuits through structural graph traversal
15 years 24 days ago
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www.ece.iit.edu
Level-sensitive transparent latches are widely used in high-performance sequential circuit designs. Under process variations, the timing of a transparently latched circuit will ada...
Xingliang Yuan, Jia Wang
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