Sciweavers

TC
2002
13 years 7 months ago
Hybrid Load-Value Predictors
Martin Burtscher, Benjamin G. Zorn
MICRO
1995
IEEE
102views Hardware» more  MICRO 1995»
13 years 11 months ago
Zero-cycle loads: microarchitecture support for reducing load latency
Untolerated load instruction latencies often have a significant impact on overall program performance. As one means of mitigating this effect, we present an aggressive hardware-b...
Todd M. Austin, Gurindar S. Sohi
ISCA
1999
IEEE
124views Hardware» more  ISCA 1999»
13 years 11 months ago
Speculation Techniques for Improving Load Related Instruction Scheduling
State of the art microprocessors achieve high performance by executing multiple instructions per cycle. In an out-oforder engine, the instruction scheduler is responsible for disp...
Adi Yoaz, Mattan Erez, Ronny Ronen, Stéphan...
IPPS
2003
IEEE
14 years 20 days ago
Using Incorrect Speculation to Prefetch Data in a Concurrent Multithreaded Processor
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...
Ying Chen, Resit Sendag, David J. Lilja
IISWC
2006
IEEE
14 years 1 months ago
Load Instruction Characterization and Acceleration of the BioPerf Programs
The load instructions of some of the bioinformatics applications in the BioPerf suite possess interesting characteristics: only a few static loads cover almost the entire dynamic ...
Paruj Ratanaworabhan, Martin Burtscher