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ASPDAC
2000
ACM
83views Hardware» more  ASPDAC 2000»
15 years 2 months ago
Low-power design of sequential circuits using a quasi-synchronous derived clock
– This paper presents a novel circuit design technique to reduce the power dissipation in sequential circuits by generating a quasi-synchronous derived clock from the master cloc...
Xunwei Wu, Jian Wei, Massoud Pedram, Qing Wu