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MEMOCODE
2003
IEEE
13 years 11 months ago
Optimizations for Faster Execution of Esterel Programs
Several efficient compilation techniques have been recently proposed for the generation of sequential (C) code from Esterel programs. Consisting essentially in direct simulation ...
Dumitru Potop-Butucaru, Robert de Simone
MEMOCODE
2003
IEEE
13 years 11 months ago
Executable Computational Logics: Combining Formal Methods and Programming Language Based System Design
An executable computational logic can provide the desired bridge between formal system properties and formal methods to verify them on the one hand, and executable models of syste...
José Meseguer
MEMOCODE
2003
IEEE
13 years 11 months ago
Methods for exploiting SAT solvers in unbounded model checking
— Modern SAT solvers have proved highly successful in finding counterexamples to temporal properties of systems, using a method known as ”bounded model checking”. It is natu...
Kenneth L. McMillan
MEMOCODE
2003
IEEE
13 years 11 months ago
MoDe: A Method for System-Level Architecture Evaluation
System-level design methodologies for embedded HW/SW systems face several challenges: In order to be susceptible to systematic formal analysis based on state-space exploration, a ...
Jan Romberg, Oscar Slotosch, Gabor Hahn
MEMOCODE
2003
IEEE
13 years 11 months ago
Real-time Property Preservation in Approximations of Timed Systems
Formal techniques have been widely applied in the design of real-time systems and have significantly helped detect design errors by checking real-time properties of the model. Ho...
Jinfeng Huang, Jeroen Voeten, Marc Geilen
MEMOCODE
2003
IEEE
13 years 11 months ago
Bridging CSP and C++ with Selective Formalism and Executable Specifications
CSP (Communicating Sequential Processes) is a useful algebraic notation for creating a hierarchical behavioural specification for concurrent systems, due to its formal interproces...
William B. Gardner
MEMOCODE
2003
IEEE
13 years 11 months ago
LOTOS Code Generation for Model Checking of STBus Based SoC: the STBus interconnect
In the design process of SoC (System on Chip), validation is one of the most critical and costly activity. The main problem for industrial companies like STMicroelectronics, stand...
Pierre Wodey, Geoffrey Camarroque, Fabrice Baray, ...
MEMOCODE
2003
IEEE
13 years 11 months ago
Exact Runtime Analysis Using Automata-Based Symbolic Simulation
In this paper, we present a technique for determining tight bounds on the execution time of assembler programs. Thus, our method is independent of the design flow, but takes into...
Tobias Schüle, Klaus Schneider