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ASPDAC
2001
ACM
107views Hardware» more  ASPDAC 2001»
13 years 9 months ago
An efficient solution to the storage correspondence problem for large sequential circuits
Abstract- Traditional state-traversal-basedmethods for verifying sequential circuits are computationally infeasible for circuits with a large number of memory elements. However, if...
Wanlin Cao, D. M. H. Walker, Rajarshi Mukherjee
DATE
2006
IEEE
84views Hardware» more  DATE 2006»
13 years 11 months ago
Vulnerability analysis of L2 cache elements to single event upsets
Memory elements are the most vulnerable system component to soft errors. Since memory elements in cache arrays consume a large fraction of the die in modern microprocessors, the p...
Hossein Asadi, Vilas Sridharan, Mehdi Baradaran Ta...
IOLTS
2008
IEEE
102views Hardware» more  IOLTS 2008»
13 years 12 months ago
Integrating Scan Design and Soft Error Correction in Low-Power Applications
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...
Michael E. Imhof, Hans-Joachim Wunderlich, Christi...